Power Aware CDC Verification at RTL for Faster SoC Verification Closure

Innovations in design technologies and verification methodologies are creating complex SoCs that operate at very high speeds while incorporating optimal power management strategies to reduce power consumption. Design size inches towards multi-billion gates and designs incorporate multiple asynchronous clocks, IO-interfaces, cores and peripherals. The ever-increasing counts of asynchronous clocks—coupled with tight power constraints—pose interesting verification challenges that cannot be overlooked.